Publications

R. Mann’s citations (based on googles citation tracker)

[1] R. Mann, R. Baxter, W. Tice, S. Friedmann, ” Low Temperature Nitridation of TiSi2″, Extended Abstracts of the fall meeting of the Electrochemical Soc.,Honolulu, Hawai, 13-23 Oct., 87-2 p.974-975 (1987).

[2] L. Borucki, R. Mann, G. Miles, J. Slinkman and T. Sullivan,”A Model for Titanium Silicide Film Growth” in Proc. International Electron Devices Meeting IEDM ’88. Technical Digest, 1988, pp. 348–351.

[3] E. Nowak, A. Bhattacharyya, A. Klett, and R. W. Mann, “Subhalf-Micron Buried-Channel PFET Design Considerations” IEEE Transactions on Electron Devices, vol. 35, no. 12, p. 2430, Dec 1988.

[4] A. Bhattacharyya, R. Mann, E. Nowak, R. Piro, J. Springer, S. Springer, and D. Wong, “A half-micron manufacturable high performance cmos technology applicable for multiple power supply applications,” in Proc. Technical Papers VLSI Technology, Systems and Applications 1989 International Symposium on, 1989, pp. 321–326.

[5] R. W. Mann, C. A. Racine, and R. S. Bass, “Nucleation, Transformation and Agglomeration of C54 Phase Titanium Disilicide” Mat. Res. Soc. Symp. Proc. 224 p.115 (1991).

[6] R. W. Mann, C. A. Racine, “Microstructure Control and Thermal Stability of Titanium Silicide” Extended Abstracts of the Spring meeting of the Electrochem. Soc., Extended abst. 272 (1992).

[7] L. A. Clevenger, J.M.E Harper, C. Cabral, C. Nobili, G. Ottaviani, R. W. Mann, “Kinetic analysis of C49-TiSi2 and C54-TiSi2 formation at rapid thermal annealing rates” J.Appl.Phys. 72 (10) p.4978-4980 (1992).

[8] L. Clevenger, Q. Hong, R. Mann, and J. Harper, “Silicide formation in Ti-Si and Co-Si reactions,” in MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS, 1993.

[9] R. W. Mann, L. A. Clevenger and Q. Z. Hong, “The C49 to C54-TiSi2 transformation in self-aligned silicide C54-TiSi2 transformation in self-aligned silicide applications“, J. Appl. Phys. 73 (7) p.3566-3568 (1993).

[10] R. W. Mann, L. A. Clevenger and Q. Z. Hong, “Phase transformation Kinetics of TiSi2”, Mat. Res. Soc. Symp. Proc. :311 p.281-286 (1993).

[11] L. A.Clevenger, Q. Z. Hong, R. W. Mann, K. Barmak, C.Cabral,Jr., C. Nobili and G. Ottaviani, “Silicide Formation in Ti-Si and Co-Si Reactions”, Mat. Res. Soc. Symp. Proc. 311 p.253-262 (1993).

[12] R. W. Mann, L. A. Clevenger “The C49 to C54 Phase Transformation in TiSi2 Thin Films” J.Electrochem. Soc. 141 (5) p.1347-1350 (1994).

[13] L. A. Clevenger and R. W. Mann, “Titanium Silicides and their technological applications” Mat. Res. Soc. Symp. Proc. 320 p.15 (1994).

[14] L .A. Clevenger, R. W. Mann and J. Piccirillo, “Formation of C54-TiSi2 on doped polycrystalline silicon using one-step versus two-step annealing processes, Advanced metallization for Devices and Circuits-Science, Technology and Manufacturability, III. (1994)

[15] L. A. Clevenger, R. W. Mann, R. A. Roy, K. L. Saenger, C. Cabral, Jr., J. Piccirillo, “Study of C49-TiSi2 and C54-TiSi2 formation on doped polycrystalline silicon using in-situ resistance measurements during annealing“, Advanced metallization for Devices and Circuits-Science, J.Appl.Phys., 76, 7874 (1994)

[16] Koburger, C.W., III Clark, W.F. Adkisson, J.W. Adler, E. Bakeman, P.E. Bergendahl, A.S. Botula, A.B. Chang, W. Davari, B. Givens, J.H. Hansen, H.H. Holmes, S.J. Horak, D.V. Lam, C.H. Lasky, J.B. Luce, S.E. Mann, R.W. Miles, G.L. Nakos, J.S. Nowak, E.J. Shahidi, G. Taur, Y. White, F.R. Wordeman, M.R.”A half micron CMOS logic generation “, IBM J. Res. Dev. (USA) Vol.39, No.1-2 Jan. March 1995, p.215-27.

[17] T.B.Hook, R.W.Mann, E.J.Nowak, “Titanium Silicide/Silicon Non-ohmic Contact Resitance for NFETs, PFETs, Diffused Resistors and NPNs in a BiCMOS Technology“, IEEE Trans. Electron Devices 42 no. 4, 697 (1995).

[18] R.W. Mann, L.A. Clevenger, P.D. Agnello, F.R. White,”Silicides and local interconnects for high-performance VLSI applications: a review”, IBM Journal of Res. and Dev., Vol.39, No.4 July P403-17 (1995).

[19] R.W.Mann, L.A.Clevenger, G.L.Miles, J.M.E.Harper, F.M.D’Heurle and C.Cabral,Jr., T.A.Knotts, D.W.Rakowski, “Reduction of the C54-TiSi2 Phase Formation Temperature Using Metallic Impurities“, 136 Appl. Phys. lett. 67, no.25, 3729 (1995).

[22] R. W. Mann, L. A. Clevenger, G. L. Miles, J. M. E. Harper, F. M. D’Heurle and C. Cabral, Jr., T. A. Knotts, D. W. Rakowski, “Reduction of the C54-TiSi2 Phase Formation Temperature Using Refractory metal ion implantation”, Mat. Res. Soc. Symp. Proc. 402 p.95 (1996).

[23] G. L. Miles, R. W. Mann and J. E. Bertsch, “TiSi2 phase transformation characteristics on narrow devices” Thin Solid Films 290-291, 469 (1996).

[24] Cabral, C., Jr. Clevenger, L.A. Harper, J.M.E. d’Heurle, F.M. Roy, R.A. Lavoie, C. Saenger, K.L. Miles, G.L. Mann, R.W. Nakos, J.S. “Low temperature formation of C54-TiSi2 using titanium alloys” Appl. Phys. Lett. (USA) Vol.71, No.24 15 Dec. 1997 P3531-3

[25] Cabral, C. Clevenger, L.A., Jr. Harper, J.M.E. d’Heurle,F.M. Roy, R.A. Saenger, K.L. Miles, G.L. Mann, R.W. “Lowering the formation temperature of the C54-TiSi2 phase using a metallic interfacial layer”, J. Mater. Res. (USA) Vol.12, No.2 Feb. 1997 P304-7

[26] Cabral, C., Jr. Clevenger, L.A. Harper, J.M.E. Roy, R.A. Saenger, K.L. Miles, G.L. Mann, R.W.”In situ X ray diffraction analysis of TiSi2 phase formation from a titanium molybdenum bilayer”Thin Films – Structure and Morphology. Symposium 1997 P295-301

[27] Cabral, C. Jr. Clevenger, L.A. Harper, J.M.E. Roy, R.A. Saenger, K.L. Miles, G.L. Mann, R.W. ,” In-situ X-ray diffraction analysis of TiSi2 phase formation from a titanium-molybdenum bilayer” Thin Films – Structure and Morphology Materials Research Society Symposium Proceedings v 441 1997. Materials Research Society, Pittsburgh, PA, USA. p 295-301

[28] O. Bula, D. Cole, E. Conrad, D. Coops W. Leipold, R. Mann, “Optimization Criteria for SRAM Design- Lithography Contribution”, Proceedings of SPIE – The International Society for Optical Engineering v 3679 n II 1999. p 847-859.

[29] P. Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, A. Eckert, L. Hadel, M. Hargrove, J. Herman, L.Lin, R. Mann, E. Maciejewski, S. Narasimha, P. O’Neil, S. Rauch, D.Ryan, J. Toomey, L. Tsou, P. Varekamp, R. Wachnik, T.Wagner, S. Wu, C. Yu, P. Agnello, J. Connolly, S. Crowder, C. Davis, R. Ferguson, A. Sekiguchi, L.Su, R. Goldblatt, and T.C. Chen, “A High Performance 0.13mm SOI CMOS Technology with Cu Interconnects and Low-k BEOL Dielectric“. VLSI Tech Symp paper 19.1 (2000)

[30] S. V. Kosonocky, M, Immediato, P. Cottrell, T. Hook, R. Mann, J. Brown, “Enhanced Mult-Threshold (MTCMOS) Circuits Using Variable Well Bias“, Low Power Electronics and Design, International Symposium on, 2001. 6-7 Aug. 2001 Page(s):165 – 169

[31] T. Hook, M. Brietwisch, J. Brown, P. Cottrell, D. Hoyniak, C. Lam, R. Mann, “Noise Margin and Leakage in Ultra-Low Leakage SRAM Cell Design“, IEEE Trans. Elec. Dev. Vol. 49, no. 8, Aug. 2002, p. 1499-1501

[32] Hook, T.B.; Brown, J.S.; Breitwisch, M.; Hoyniak, D.; Mann, R.; “High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step“, Electron Devices, IEEE Transactions Volume 49, Issue 9, Sept. 2002 Page(s):1623 – 1627

[33] T. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, R. Mann, “Lateral Ion Implant Straggle and Mask Proximity Effect”, IEEE Trans. Elec. Dev. Vol. 50, no. 9, Sept 2003 p. 1946-1951

[34] R. W. Mann, W. Abadeer, M. Brietwisch, O. Bula, J. Brown, B. Colwill, P.Cottrell, W. Crocco, S. Furkay, M. Hauser, T. Hook, D. Hoyniak, J. Johnson, C. Lam, R. Mih, J. Rivard, A. Moriwaki, E. Phipps, C. Putnam, B. Rainey, J. Toomey, M. Younus, “Ultralow-power SRAM technology”, IBM J. Res. & Dev. Vol. 47, no. 5/6 Sep/Nov 2003, p. 553-566

[35] Z. Luo, A. Steegen, M. Eller, R. Mann, C. Baiocco, P. Nguyen, L. Kim, M. Hoinkis, V. Ku, V. Klee, F. Jamin, P. Wrschka, P. Shafer, W. Lin, S. Fang, W. Tan, D. Park, R. Mo, J. Lian, D. Vietzke, C. Coppock, A. Vayshenker, T. Hook, V. Chan, K. Kim, A. Cowley, S. Kim, E. Kaltalioglu, B. Zhang, S. Marokkey, Y. Lin, M. Weybright, R. Rengarajan, J. Ku, T. Schiml, J. Sudijono, I. Yang, Clement Wann, “High Performance and Low Power Transistors Integrated in 65nm Bulk CMOS Technology” , Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International 13-15 Dec. 2004 Page(s):661 – 664

[36] Natzle, W.C.; Horak, D.; Deshpande, S.; Chien-Fan Yu; Liu, J.C.; Mann, R.W.; Doris, B.; Hanafi, H.; Brown, J.; Sekiguchi, A.; Tomoyasu, M.; Yamashita, A.; Prager, D.; Funk, M.; Cottrell, P.; Higuchi, F.; Takahashi, H.; Sendelbach, M.; Solecky, E.; Wendy Yan; Tsou, L.; Qingyun Yang; Norum, J.P.; Iyer, S.S.;,” Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic“, Advanced Semiconductor Manufacturing, 2004. ASMC ’04. IEEE Conference and Workshop 4-6 May 2004 Page(s):61 – 65

[37] A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye, K. Chin, “Fluctuation Limits & Scaling Opportunities for CMOS SRAM Cells” , Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International 5-7 Dec. 2005 Page(s):659 – 662

[38] Steegen, A.; Mo, R.; Mann, R.; Sun, M.-C.; Eller, M.; Leake, G.; Vietzke, D.; Tilke, A.; Guarin, F.; Fischer, A.; Pompl, T.; Massey, G.; Vayshenker, A.; Tan, W.L.; Ebert, A.; Lin, W.; Gao, W.; Lian, J.; Kim, J.-P.; Wrschka, P.; Yang, J.-H.; Ajmera, A.; Knoefler, R.; Teh, Y.-W.; Jamin, F.; Park, J.E.; Hooper, K.; Griffin, C.; Nguyen, P.; Klee, V.; Ku, V.; Baiocco, C.; Johnson, G.; Tai, L.; Benedict, J.; Scheer, S.; Zhuang, H.; Ramanchandran, V.; Matusiewicz, G.; Lin, Y.-H.; Siew, Y.K.; Zhang, F.; Leong, L.S.; Liew, S.L.; park, K.C; Lee, K.-W.; Hong, D.H.; Choi, S.-M.; Kaltalioglu, E.; Kim, S.O.; Naujok, M.; Sherony, M.; Cowley, A.; Thomas, A.; Sudijohno, J.; Schiml, T.; Ku, J.-H.; Yang, I.; “65nm cmos technology for low power applications” , Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International 5-7 Dec. 2005 Page(s):64 – 67

[39] Wann, C.; Wong, R.; Frank, D.J.; Mann, R.; Shang-Bin Ko; Croce, P.; Lea, D.; Hoyniak, D.; Yoo-Mi Lee; Toomey, J.; Weybright, M.; Sudijono, J.; “SRAM cell design for stability methodology“, VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on 25-27 April 2005 Page(s):21 – 22

[40] Benton H. Calhoun, Sudhanshu Khanna, Randy Mann, and Jiajing Wang.”Sub-threshold Circuit Design with Shrinking CMOS Devices“, International Symposium on Circuits and Systems, 2009

[41] R.W.Mann, S.Nalam, J.Wang, B.H.Calhoun, “Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM” In Proc. 11th International symposium on quality electronic design, ISQED 2010, pp.1-6.

[42] Randy W. Manna, Jiajing Wang, Satyanand Nalam, Sudhanshu Khanna, Geordie Braceras,
Harold Pilo, Benton H. Calhoun,”Impact of circuit assist methods on margin and performance in 6T SRAM” Journal of Solid State Electronics, vol. 54, no. 11, pp. 1398 – 1407, Nov 2010.

[43] Jiajing Wang, Satyanand Nalam, Zhenyu(Jerry) Qi, Randy W. Mann, Mircea Stan, and Benton H. Calhoun,”Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress” CICC, San Jose, CA, 09/2010.

[44] R.W.Mann, “Interactions of Technology and Design in Nanoscale SRAM“, Ph.D. Dissertation, Dec. 2010.

[45] R.W.Mann and B.H.Calhoun, “New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm“, In Proc. 12th International symposium on quality electronic design, ISQED 2011.

[46] R. W. Mann, T. B. Hook, P. T. Nguyen, Calhoun, B. H. Calhoun, “Non-random device mismatch considerations in nanoscale SRAM“, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 20, Issue 7, pp.1211-1220, July, 2012.

[47] Stuart N. Wooters, Adam C. Cabe, Zhenyu Qi, Wang J, Randy W. Mann, Benton H. Calhoun, Mircea R. Stan, Travis N. Blalock, “Tracking On-Chip Age Using Distributed,Embedded Sensors” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, Issue 11, pp.1974-1985, Nov., 2012.

[48] Huiling Shang; Jain, S.; Josse, E.; Alptekin, E.; Nam, M.H.; Kim, S.W.; Cho, K.H.; Kim, I.; Liu, Y.; Yang, X.; Wu, X.; Ciavatti, J.; Kim, N.S.; Vega, R.; Kang, L.; Meer, H.V.; Samavedam, S.; Celik, M.; Soss, S.; Utomo, H.; Ramachandran, R.; Lai, W.; Sardesai, V.; Tran, C.; Kim, J.Y.; Park, Y.H.; Tan, W.L.; Shimizu, T.; Joy, R.; Strane, J.; Tabakman, K.; Lalanne, F.; Montanini, P.; Babich, K.; Kim, J.B.; Economikos, L.; Cote, W.; Reddy, C.; Belyansky, M.; Arndt, R.; Kwon, U.; Wong, K.; Koli, D.; Levedakis, D.; Lee, J.W.; Muncy, J.; Krishnan, S.; Schepis, D.; Chen, X.; Kim, B.D.; Tian, C.; Linder, B.P.; Cartier, E.; Narayanan, V.; Northrop, G.; Menut, O.; Meiring, J.; Thomas, A.; Aminpur, M.; Park, S.H.; Lee, K.Y.; Kim, B.Y.; Rhee, S.H.; Hamieh, B.; Srivastava, R.; Koshy, R.; Goldberg, C.; Pallachalil, M.; Chae, M.; Ogino, A.; Watanabe, T.; Oh, M.; Mallela, H.; Codi, D.; Malinge, P.; Weybright, M.; Mann, R.; Mittal, A.; Eller, M.; Lian, S.; Li, Y.; Divakaruni, R.; Bukofsky, S.; Kim, J.D.; Sudijono, J.; Neumueller, W.; Matsuoka, F.; Sampson, R.; , “High performance bulk planar 20nm CMOS technology for low power mobile applications”, VLSI Technology (VLSIT), 2012 Symposium on , vol., no., pp.129-130, 12-14 June 2012

[49] Balasubramanian, S., Vinayak Joshi, T. Klick, R. Mann, J. Versaggi, Anjali Gautam, C. Weintraub et al. “HTOL SRAM Vmin shift considerations in scaled HKMG technologies.” In Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the, pp. 1-4. IEEE, 2014.

[50] Jianhua Yin; Fernandes, S.; Yinzhe Ma; Sheng Xie; Xuemei Liu; Qiushi Wang; Dexter, M.; Meixiong Zhao; Mann, R.; Chong Khiam Oh; Tay, M.; Lim, S.K.; Dapeng Sun; Chao, P.; Lam, J., “Advanced soft fail characterization methodology for sub-28nm nanoscale SRAM yield improvement,” in Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI , vol., no., pp.351-356, 19-21 May 2014

[51] Y. Mamy Randriamihaja, W.McMahon, S.Balasubramanian, T.Nigam, B. Parameshwaran, R. Mann, T. Klick, T. Schaefer, F. Chen, A. Kumar, Y. Song, V. Joshi, R. Ranjan, “ASSESSING INTRINSIC AND EXTRINSIC END-OF-LIFE RISK USING FUNCTIONAL SRAM WAFER LEVEL TESTING”, Reliability Physics Symposium (IRPS), 2015 IEEE International, pp. 6A-5. IEEE, 2015.

[52] R. W. Mann and W. McMahon and Y. Mamy Randriamihaja and Y. Song and A. A. Kallianpur and S. Xie and A. Gautam and J. Versaggi and B. Parameshwaran and C. E. Weintraub, “Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-10, 2016.

[53] H. N. Patel, B. H. Calhoun and R. W. Mann, “Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications,” 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), Thessaloniki, pp. 209-210, 2017.

[54] Randy W. Mann, Sandeep Puri, Sheng Xie, Daniel Marienfeld, Joseph Versaggi, Bianzhu Fu, Michael Gribelyuk, Ratheesh R. Thankalekshmi, Xiaoqiang Zhang, Hui Zang, and Chad E. Weintraub, “Array Termination Impacts in Advanced SRAM,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2449-2457, Sept. 2017.

[55] Paul, Bipul C and Jacob, Ajey P and Taylor, William and Mann, Randy and Versaggi, Joe and Nowak, Edward and Liebmann, Lars W, “A Retrospective View on the Technology Evolution to Support Low Power Mobile Application” ,Journal of Low Power Electronics, volume 14,number 3, pp. 374-392, 2018.

[56] Yuncheng Song, Randy Mann, Sheng Xie, Lucile C. Teague Sheridan, Joseph Versaggi, Dapeng Sun, Chong Khiam Oh, Dirk Fimmel, Daniel Marienfeld, Matthias Hoffmann, Wolfgang Finger, “Direct insight to SRAM array devices in advanced FinFET nodes by large scale ultra-fast in-situ characterization”, International Memory Workshop (IMW) May 2019.

[57] Randy W. Mann, Meixiong Zhao, Sanjay Parihary, Qun Gao, Ankur Arya, Carl Radens, Shesh M. Pandey, Joseph Versaggi, Jack Higman, Rick Carter, “An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 8, pp. 1819-1827, Aug. 2019.
doi: 10.1109/TVLSI.2019.2907594

[58] Randy W. Mann, Meixiong Zhao, Sanjay Parihary, O Sung Kwon, Xi Cao, Sanjay Parihar, Muhammed Ahosan Ul Karim, Joseph Versaggi, Jack Higman, Rick Carter, “Bias-Dependent Variation in FinFET SRAM,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
doi: 10.1109/TVLSI.2020.2974202