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#PATENTDESCRIPTION
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10710,818,674Structures and SRAM bit cells integrating complementary field-effect transistors
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10610,629,602Static random access memory cells with arranged vertical-transport field-effect transistors
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10510,497,692SRAM structure with alternate gate pitches
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10410,439,064Dual port vertical transistor memory cell
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10310,403,629Six-transistor (6T) SRAM cell structure
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10,332,897
Method of reducing fin width in FinFet SRAM array to mitigate low voltage strap bit fails
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10110,163,914Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails
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10010,109,637Cross couple structure for vertical transistors
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9910,068,902
Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method
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9810,068,660
Methods, apparatus, and system for global healing of write-limited die through bias temperature instability
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979916212
Method, apparatus, and system for targeted healing of write fails through bias temperature instability
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969761594Hardmask for a halo/extension implant of a static random access memory (SRAM) layout
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959704600
Method, apparatus, and system for global healing of write-limited die through bias temperature instability
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949601188
Method, apparatus and system for targeted healing of stability failures through bias temperature instability
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939601187
Method, apparatus, and system for global healing of stability-limited die through bias temperature instability
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929564375Structures and methods for extraction of device channel width
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919530488Methods, apparatus and system determining dual port DC contention margin
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909484300Device resulting from printing minimum width semiconductor features at non-minimum pitch
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899372226Wafer test structures and methods of providing wafer test structures
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889337204Memory Cell
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879263349Printing minimum width semiconductor features at non-minimum pitch and resulting device
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869219040Integrated circuit with semiconductor fin fuse
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859069922Modeling memory cell skew sensitivity
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849048136SRAM cell with individual electrical device threshold control
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839029956SRAM cell with individual electrical device threshold control
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828947912Memory cell including unidirectional gate conductors and contacts
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818907687Integrated circuit with stress generator for stressing test devices
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808597994Semiconductor device and method of fabrication
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798569116Integrated circuit with a fin-based fuse, and related fabrication method
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788563398Electrically conductive path forming below barrier oxide layer and integrated circuit
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778099688Circuit design
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767989922Highly tunable metal-on-semiconductor trench varactor
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757923840Electrically conductive path forming below barrier oxide layer and integrated circuit
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747745863Flip FERAM cell and method to form same
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737696034Methods of base formation in a BiCOMS process
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727679083Semiconductor integrated test structures for electron beam inspection of semiconductor wafers
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717466604SRAM voltage control for improved operational margins
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707402857Flip FERAM cell and method to form same
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697390721Methods of base formation in a BiCMOS process
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687313032SRAM voltage control for improved operational margins
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677217969Flip FERAM cell and method to form same
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667193262Low-cost deep trench decoupling capacitor device and process of manufacture
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657190007Isolated fully depleted silicon-on-insulator regions by selective etch
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647186573Flip FERAM cell and method to form same
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637166904Structure and method for local resistor element in integrated circuit technology
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627087486Method for scalable, low-cost polysilicon capacitor in a planar DRAM
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617087477FinFET SRAM cell using low mobility plane for cell stability and method for forming
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607075153Grounded body SOI SRAM cell
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597057180Detector for alpha particle or cosmic ray
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587005334Zero threshold voltage pFET and method of making same
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576967351Finfet SRAM cell using low mobility plane for cell stability and method for forming
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566965133Method of base formation in a BiCMOS process
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556962838High mobility transistors in SOI and method for forming
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546946376Symmetric device with contacts self aligned to gate
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536917221Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits
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526900505Method of forming refractory metal contact in an opening, and resulting structure
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516891419Methods and apparatus for employing feedback body control in cross-coupled inverters
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506881672Selective silicide blocking
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496825530Zero Threshold Voltage pFET and method of making same
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486815751Structure for scalable, low-cost polysilicon DRAM in a planar capacitor
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476778449Method and design for measuring SRAM array leakage macro (ALM)
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466774017Method and structures for dual depth oxygen layers in silicon-on-insulator processes
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456762121Method of forming refractory metal contact in an opening, and resulting structure
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446700163Selective silicide blocking
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436646305Grounded body SOI SRAM cell
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426624478High mobility transistors in SOI and method for forming
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416624475SOI low capacitance body contact
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406614124Simple 4T static ram cell for low power CMOS applications
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396555859Flip FERAM cell and method to form same
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386515317Sidewall charge-coupled device with multiple trenches in multiple wells
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376512296Semiconductor structure having heterogenous silicide regions having titanium and molybdenum
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366498096Borderless contact to diffusion with respect to gate conductor and methods for fabricating
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356489223Angled implant process
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346476445Method and structures for dual depth oxygen layers in silicon-on-insulator processes
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336445050Symmetric device with contacts self aligned to gate
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326441410MOSFET with lateral resistor ballasting
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316420746Three device DRAM cell with integrated capacitor and local interconnect
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306395624Method for forming implants in semiconductor fabrication
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296387596Method of forming resist images by periodic pattern removal
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286380063Raised wall isolation device with spacer isolated contacts and the method of so forming
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276368903SOI low capacitance body contact
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266338921Mask with linewidth compensation and method of making same
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256335272Buried butted contact and method for fabricating
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246333202Flip FERAM cell and method to form same
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236300228Multiple precipitation doping process
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226294419Structure and method for improved latch-up using dual depth STI with impurity implant
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216268286Method of fabricating MOSFET with lateral resistor with ballasting
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206215190Borderless contact to diffusion with respect to gate conductor and methods for fabricating
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196187679Low temperature formation of low resistivity titanium silicide
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186187617Semiconductor structure having heterogeneous silicide regions and method for forming same
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176153934Buried butted contact and method for fabricating
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166144086Structure for improved latch-up using dual depth STI with impurity implant
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156140171FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication
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146022766Semiconductor structure incorporating thin film transistors, and methods for its manufacture
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136008112Method for planarized self-aligned floating gate to isolation
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125899713Method of making NVRAM cell with planar control gate
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115828131Low temperature formation of low resistivity titanium silicide
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105757050Field effect transistor having contact layer of transistor gate electrode material
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95744384Semiconductor structures which incorporate thin film transistors
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85677563Gate stack structure of a field effect transistor
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75675185Semiconductor structure incorporating thin film transistors with undoped cap oxide layers
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65672901Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
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55670812Field effect transistor having contact layer of transistor gate electrode material
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45510295Method for lowering the phase transformation temperature of a metal silicide
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35496771Method of making overpass mask/insulator for local interconnects
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25485095Fabrication test circuit and method for signalling out-of-spec resistance in integrated circuit structure
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15453400Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits